1. Field of the Invention
The present invention concerns a semiconductor memory device, and more particularly a parallel bit test circuit for testing the memory cells in parallel bits.
2. Description of the Related Art
As a semiconductor memory device is more highly integrated, the time required for testing the memory cells is more increased, and thus the testing cost. For example, if the number of the memory cells of a tested memory device is N (natural number and the number of the data I/O (input/output) terminals "m" (natural number), the data read or write operation must be performed N/m times to access all the memory cells. However, in this case, if the data read or write operation can be carried out simultaneously for "n" (natural number) memory cells through each of the "m" I/O terminals, "N/(m.times.n)" times of performing the operation suffice accessing all the memory cells, reducing the test time to 1/n. This is called the parallel bit test or multi bit test.
Referring to FIGS. 1A and 1B for illustrating a conventional parallel bit test circuit, there are shown four memory cell arrays, each of which has a common word line and a common column selection line and a plurality of data I/O lines respectively connected with the memory cells. In this case, the number "m" of the I/O terminals is 4 and the number "n" of the tested memory cells also 4. For example, the first array "0" has four memory cells C00, C01, C02 and C03 commonly connected with the word line WL0 and column selection line CSL0 and with respective data I/O lines IO00, IO01, IO02 and IO03. The data of the four memory cells C00, C01, C02 and C03 are applied through their respective I/O lines IO00, IO01, IO02 and IO03 to a comparator consisting of an AND gate 100, NOR gate 101 and OR gate 102, which performs the operation for testing the memory cells as follows:
At first, if the four memory cells are all written with data "0" and there exists a failed cell, the data of the failed cell is read as "1" so as to cause the comparator to produce the data signal "0" representing the fail transferred to the data I/O terminal DQ0. If there is no failed cell, all the four memory cells are read as "0", thus transferring the data signal "1" representing no fail to the I/O terminal DQ0. Alternatively, if the four memory cells all written data "1" and there exists a failed cell, the data of the failed cell is read as "0" so as to cause the comparator to produce the data signal "0" representing the fail transferred to the data I/O terminal DQ0. If there is no failed cell, all the four memory cells are read as "1", thus transferring the data signal "1" representing no fail to the I/O terminal DQ0.
Thus, each of the four data I/O lines is used for simultaneously testing four data so that 16 bits (m.times.n) are tested in parallel reducing the test time to 1/n, i.e., 1/4. However, the comparator may normally work provided all the four memory cells are normal or up to three memory cells are failed. Otherwise, if all the four memory cells are failed, the comparator fails to produce the data signal "0" representing the fail, but instead the data signal "1" representing no fail. For example, if the four memory cells are written with data "0" and all failed, the data of all the four memory cells are read as "1" so as to cause the comparator to produce the data "1". Alternatively, if the four memory cells are written with data "1" and all failed, the data of all the four memory cells are read as "0" so as to cause the comparator to produce the data "1". It is frequently caused by the word line stuck that the four memory cells are all failed.